As part of a class in my master’s program in Electrical Engineering, we were asked to create an OFDM transmitter/channel/receiver in Matlab. In our next class we also created the transmitter in Verilog HDL for an Altera Stratix FPGA. This is a that project.
Since this was a very interesting project for me I thought I’d share my code, hopefully it will benefit someone.
The transmitter is a very simplified design, with an FFT size of 256, Cyclic Prefix of 96 and a Roll off of 32. A random number generator creates a sequence of bits which are converted into QPSK symbols. After running through a FFT, the cyclic prefix and roll off are appended and prepended to the sequence. This was one of the most interesting parts as it required creating a secondary clock which ran at (256+96+32)/256 (or 1.5) times the original clock rate. The FFT output, now stored in RAM, was accessed in such a way that the cyclic prefix and roll off were added to the original sequence.
I should note that this is in no way a finished project, but does demonstrate the a starting point for implementing the DOCSIS 3.1 standard. One of the most difficult parts of implementing this project is keeping track of every single bit, especially when switching clock speeds. Modelsim was very helpful in this.
Likely the most challenging part of this project was the very long compile times. It is very much well worth your time to read the compiler documentation. Anything that can increase your compile times is going to save you a huge amount of time.
The repository is located here.